ADT7473
Table 82. LOCAL TEMPERATURE OFFSET REGISTER (0X71)
Register Address
<7:0>
R/W (Note 1)
R/W
Description
Allows a twos complement offset value to be automatically added to
or subtracted from the local temperature reading. LSB value = 0.5 ? C.
Power-On Default
0x00
1. This register becomes read-only when the Configuration Register 1 Lock bit is set to 1. Any further attempts to write to this register have
no effect.
Table 83. REMOTE 2 TEMPERATURE OFFSET REGISTER (0X72)
Register Address
<7:0>
R/W (Note 1)
R/W
Description
Allows a twos complement offset value to be automatically added to
or subtracted from the Remote 2 temperature reading. This is to
compensate for any inherent system offsets such as PCB trace
resistance. LSB value = 0.5 ? C.
Power-On Default
0x00
1. This register becomes read-only when the Configuration Register 1 Lock bit is set to 1. Any further attempts to write to this register have
no effect.
Table 84. REGISTER 0X73 ? CONFIGURATION REGISTER 2 (POWER-ON DEFAULT = 0X00)
Bit No.
<0>
<1>
<2>
<3>
<4>
<5>
<6>
Mnemonic
FanPresDT
Fan1Detect
Fan2Detect
Fan3Detect
AVG
ATTN
CONV
R/W (Note 1)
R/W
Read-only
Read-only
Read-only
R/W
R/W
R/W
Description
When FanPresenceDT = 1, the state of Bits <3:1> of Register 0x73 reflects the presence of a
4-wire fan on the appropriate TACH channel.
Fan1 Detect = 1 indicates a 4-wire fan is connected to the PWM1 input.
Fan1 Detect = 1 indicates a 4-wire fan is connected to the PWM2 input.
Fan1 Detect = 1 indicates a 4-wire fan is connected to the PWM3 input.
AVG = 1, averaging on the temperature and voltage measurements is turned off. This allows
measurements on each channel to be made much faster.
ATTN = 1, the ADT7473/ADT7473 ? 1 removes the attenuators from the V CCP input. The
V CCP input can be used for other functions such as connecting up external sensors.
CONV = 1, the ADT7473/ADT7473 ? 1 is put into a single-channel ADC conversion mode. In
this mode, the ADT7473/ADT7473 ? 1 can be made to read continuously from one input only,
for example, Remote 1 temperature. The appropriate ADC channel is selected by writing to
Bits <7:5> of TACH1 minimum high byte register (0x55).
Bits <7:5>, Register 0x55
000
001
010
011
100
101
110
111
Reserved
V CCP
V CC (3.3 V)
Reserved
Reserved
Remote 1 Temperature
Local Temperature
Remote 2 Temperature
<7>
Shutdown
R/W
SHDN = 1, ADT7473/ADT7473 ? 1 goes into shutdown mode. All PWM outputs assert low or
high, depending on the state of the INV bit, to switch off all fans.
1. This register becomes read-only when the Configuration Register 1Lock bit is set to 1. Any further attempts to write to this register have no
effect.
Table 85. REGISTER 0X74 ? INTERRUPT MASK REGISTER 1 (POWER-ON DEFAULT = 0X00)
Bit No.
<1>
<2>
<4>
<5>
<6>
<7>
Mnemonic
V CCP
V CC
R1T
LT
R2T
OOL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
V CCP = 1, masks SMBALERT for out-of-limit conditions on the V CCP channel.
V CC = 1, masks SMBALERT for out-of-limit conditions on the V CC channel.
R1T = 1, masks SMBALERT for out-of-limit conditions on the Remote 1 temperature channel.
LT = 1, masks SMBALERT for out-of-limit conditions on the local temperature channel.
R2T = 1, masks SMBALERT for out-of-limit conditions on the Remote 2 temperature channel.
OOL = 0, then when one or more alerts are generated in Interrupt Status Register 2, assuming
all the mask bits in the Interrupt Mask Register 2 (0x75) = 1, SMBALERT are still asserted.
OOL = 1, then when one or more alerts are generated in Interrupt Status Register 2, assuming
all the mask bits in the Interrupt Mask Register 2 (0x75) = 1, SMBALERT are not asserted.
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